The Verilog Programming Language Interface, commonly called the Verilog PU, is one of the more powerful features of Verilog. The PU provides a means for both hardware designers and software engineers to interface their own programs to commercial Verilog simulators. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired. Just a few of the common uses of the PU include interfacing Veri log simulations to C language models, adding custom graphical tools to a simulator, reading and writing proprietary file formats from within a simulation, performing test coverage analysis during simulation, and so forth. The applications possible with the Verilog PLI are endless. Intended audience: this book is written for digital design engineers with a background in the Verilog Hardware Description Language and a fundamental knowledge of the C programming language. It is expected that thereader: Has a basic knowledge of hardware engineering, specifically digital design of ASIC and FPGA technologies. Is familiar with the Verilog Hardware Description Language (HDL), and can write models of hardware circuits in Verilog, can write simulation test fixtures in Verilog, and can run at least one Verilog logic simulator. Knows basic C-language programming, including the use of functions, pointers, structures and file I/O. Explanations of the concepts and terminology of digital

Table of Contents:
Introduction: The VPI and TF/ACC Parts of the Verilog PLI Standard.- 1: Creating PLI Applications Using VPI Routines.- 2: Interfacing VPI PLI Applications to Verilog Simulators.- 3: How to Use the VPI Routines.- 4: Details about the VPI Routine Library.- 5: Reading and Modifying Values Using VPI Routines.- 6: Synchronizing to Verilog Simulations Using VPI Callbacks.- 7: Interfacing to C Models Using VPI Routines.- 8: Creating PLI Applications Using TF and ACC Routines.- 9: Interfacing TF/ACC PLI Applications to Verilog Simulators.- 10: How to Use the TF Routines.- 11: Reading and Writing Values Using TF Routines.- 12: Synchronizing to Verilog Simulations Using Misctf Routines.- 13: Interfacing to C Models Using TF Routines.- 14: How to Use the ACC Routines.- 15: Details on the ACC Routine Library.- 16: Reading and Modifying Values Using ACC Routines.- 17: Synchronizing to Simulations Using the Value Change Link.- 18: Interfacing to C Models Using ACC Routines.- Appendices.- Appendix A:Linking PLI Applications to Verilog Simulators.- A.1 The PLI Interface Mechanism.- A.2 Linking PLI app’s to the Cadence Verilog-XL simulator.- A.3 Linking to NC-Verilog from Cadence Design Systems, Inc..- A.4 Linking PLI applications to the Model Technology ModelSim simulator.- A.5 Linking PLI applications to the Avant! Polaris simulator.- A.6 Linking to Silos III from Simucad, Inc..- A.7 Linking to VCS from Synopsys, Inc.- A.8 Linking to VeriBest from VeriBest, Inc.- A.9 Summary.- Appendix B: The IEEE 1364–1995 VPI Routine Library.- B.1 VPI Objects Relationships.- B.2 VPI routine definitions (listed alphabetically).- Appendix C: The IEEE 1364–1995 TF Routine Library.- C.1 TF routine definitions (listed alphabetically).- Appendix D: The IEEE 1364–1995 ACC Routine Library.- D.1 ACC Objects Relationships.- D.2 ACC routine definitions (listed alphabetically).